Sigma delta modulators or sigma delta analog/digital converters are being increasingly used to replace conventional analog/digital converter architectures in applications, where analog/digital conversion with high resolution and at the same time enhanced linearity is required. The special linearity of sigma delta modulators moreover means that sigma delta modulators are very well suited for realization in CMOS circuit technology. In addition, the dynamic range of the sigma delta modulator can be increased by multi-bit quantization, whereby a further consequence of multi-bit quantization is improved system stability.
A digital/analog converter (D/A converter) is used in the feedback path of sigma delta modulators, for which high linearity is required. The non-linearity of D/A converters can be corrected in sigma delta modulators for example by digital self-calibration of the sigma delta modulator, which however entails greater complexity of circuit design. A further concept for improving the non-linearity of not ideal D/A converters is the use of a so-called “dynamic element matching” algorithm.
FIG. 7 shows a simplified block diagram of a sigma delta modulator and/or a sigma delta A/D converter with “dynamic element matching”. The sigma delta modulator shown in FIG. 7 serves to convert an analog and time-continuous input signal x(t) into a corresponding digital time-discrete output signal y[n]. For this purpose, the sigma delta modulator comprises a forward path with an integrator 1 and a quantizer 2, whereby both a 1 bit quantizer and a multi-bit quantizer can be used. The time-discrete output signal z[n] quantized by the quantizer 2 is fed to a low-pass (LP) filter 3, on whose output the desired digital output signal y[n] is finally provided. Furthermore, the output signal of the quantizer 2 is fed back via a feedback path with a D/A converter device 6 to the input of the sigma delta modulator, whereby the analog output signal z(t) generated by the D/A converter device 6 is subtracted as shown in FIG. 7 from the analog input signal x(t), in order to feed the differential signal resulting therefrom to the integrator 1. Here, it is assumed that in the feedback path not ideal, that is to say not completely linear, D/A conversion is carried out, i.e. the D/A converter device 6 comprises a not ideal D/A converter 5. For compensation of the non-linearity of this non-linear D/A converter 5 the D/A converter device 6 also comprises a conversion element selection logic 4, which by application of a “dynamic element matching” algorithm triggers the individual D/A conversion elements of the D/A converter (DAC) 5 in such a manner that the conversion errors are averaged out as much as possible over several sampling runs. By means of the selection process of the conversion element selection logic 4 the in-band signal interference can be substantially reduced due to the non-linearity of the D/A converter 5. The aim of “dynamic element matching” is to average out matching errors of the individual D/A levels of the not ideal D/A converter 5 in such a manner that the non-linear distortion is converted into broadband noise, where it can be filtered out later. This is equivalent to an increase in the effective resolution after the filter operation.
Up till now various concepts have been proposed as “dynamic element matching” algorithms. In accordance with a first concept it was proposed that the conversion elements of the D/A converter 5 are selected in arbitrary and/or random order, that is to say the conversion elements are not selected according to a pre-determined pattern. By way of this concept, the linearity can be improved, since due to the fact that the distortion of the non-linear D/A converter 5 is distributed evenly over the entire frequency spectrum, only part of the noise falls into the base-band. In accordance with a further concept, which is also known as clocked averaging, for selecting the conversion elements of the not ideal D/A converter 5 a start index is used, which is incremented by the sampling cycle. With this concept, each conversion element is used at a minimum rate, which corresponds to the quotient resulting from the sampling rate and the total number of conversion elements. In the case of this concept the noise resulting from multiples of this minimum rate is concentrated and otherwise virtually evenly distributed over the other frequencies. Beside the concepts described above individual level averaging (ILA) has also been proposed, whereby with this concept in contrast to clocked averaging (CLA) an individual start index is used for each conversion level of the D/A converter 5. Thus, for each conversion level the error caused thereby can be averaged out after several repeated demands of the same conversion level and thus reduced to almost zero.
Apart from the concepts for a “dynamic element matching” algorithm described above a concept to improve the linearity of multi-bit sigma delta modulators and/or the D/A converters used therein, which is called data weighted averaging (DWA) has also been proposed. In accordance with this concept all conversion elements of the D/A converter 5 are operated at the maximum rate, whereby at the same time it is ensured that each conversion element is used as often as possible. This is achieved by the fact that the conversion elements are sequentially selected for each conversion operation in such a manner that said operation starts with the next available unused conversion element.
This principle will be described below by way of example on the basis of FIG. 8A–FIG. 8C, whereby it is assumed that a digital word to be converted into a corresponding analog output signal is fed to a 3 bit D/A converter 5, comprising a plurality of conversion elements 7, that in the case of the example illustrated are shown in the form of current sources and are switched in parallel between an input terminal, which is connected to a positive supply voltage VDD and an output terminal, which is connected to a negative supply voltage VSS or earth. The bit width of the D/A converter 5 thus amounts to B=3. Dependent on the value of the 3 bit digital word supplied a corresponding number of conversion elements 7 of the D/A converter 5 is activated, that is to say by triggering controllable switches allocated accordingly between the supply voltage connection VDD and the earth connection, so that an analog output signal is generated by the D/A converter 5, which corresponds to the sum of the current signals generated by the individual activated conversion elements 7. For a B bit D/A converter 5 therefore a total number of N=2b−1 conversion elements 7 is necessary, in order to cover the entire range of values of the B bit digital word. In the case of the example illustrated N=7 applies.
As shown in FIG. 8 first it is assumed that a digital word with the bit sequence “011” is fed to the D/A converter 5, which corresponds to the decimal value “3”, so that in accordance with FIG. 8A the first three conversion elements 7 of the D/A converter 5 are selected and activated accordingly, while the other conversion elements remain deactivated. In FIG. 8A the state and/or activation/deactivation of the individual conversion elements 7 of the D/A converter 5 is indicated by an array of boxes, whereby a box is allocated to each conversion element 7. A hatched box means that the corresponding conversion element has been activated and selected, while a blank box means that the corresponding conversion element has not been selected and is therefore deactivated.
In accordance with FIG. 8B a digital word with the bit sequence “001” corresponding to the decimal value “1” is subsequently fed to the D/A converter 5, whereby in FIG. 8B it is shown that the next and previously unused conversion element 7 of the D/A converter 5 is selected accordingly, while all other conversion elements are deactivated.
Finally, in accordance with FIG. 8C it is assumed that a digital word with the bit sequence “101”, which corresponds to the decimal value “5”, is fed to the D/A converter 5. Accordingly, the next five previously unused conversion elements 7 are selected for the corresponding conversion operation, whereby due to the fact that at the end only three conversion elements 7 are still available, said operation starts again cyclically at the beginning of the conversion elements 7, that is to say apart from the last three conversion elements 7 the first two conversion elements 7 of the D/A converter 5 are also selected.
From the above description, it is evident that this concept totally depends on the data sequence, thus explaining the designation “data weighted averaging”. The use linked with this concept of the individual conversion elements 7 operating at the maximum rate ensures that rapid averaging out of the errors of the D/A converter 5 can be achieved, which means that accordingly the distortion caused by the non-linearity of the D/A converter 5 can be moved into the high frequency range, where it can be easily filtered out.
For supplementary explanation of the “data weighted averaging” algorithm FIG. 9 shows for a 3 bit D/A converter with consequently seven conversion elements (that is to say B=3, N=7) a comparison of linear addressing and/or linear selection (see FIG. 9A) with addressing and/or selection in accordance with the “data weighted averaging” algorithm (see FIG. 9B), whereby similar to FIG. 8 it is assumed that the digital words are fed to the D/A converter in chronological order from top to bottom. The corresponding decimal value, which corresponds to an input and/or control code for the conversion elements, is illustrated for each digital word supplied. In the case of linear addressing, the conversion elements are selected in each case beginning with the first conversion element (according to the left column of FIG. 9A), while in the case of the “data weighted averaging” algorithm the conversion elements are selected in each case with the next free, that is to say previously unused, conversion element.
If a “data weighted averaging” algorithm or any other kind of “dynamic element matching” algorithm is used in a time-continuous application, for example in a time-continuous and oversampling sigma delta modulator with “switched capacitor” (SC) technology or in a current-steering D/A converter (DAC), any asymmetry in the states of the individual conversion elements causes non-linear distortion. This asymmetry for example could be a different rise or fall time of the current connected in each case or, if the current of the particular conversion element changes from one output to another output, an unequal connection fault in relation to the opposite direction. SC implementations however do not have the problem of data-dependent interference, since only the steady state final value is important.
In the case of a current-steering D/A converter with N conversion elements the input and/or control code can vary between 0 and N, dependent on how many of the conversion elements should be activated. An input code with the decimal value “0” means that none of the conversion elements are selected and/or activated and therefore no output current of any conversion element contributes to the output signal of the D/A converter, while an input code of N means that all conversion elements are switched through to the output of the D/A converter.
The problem of asymmetry of the type described above will be described below in detail on the basis of FIG. 10, whereby a sine wave, to which a “data weighted averaging” algorithm where N=7 is applied, is illustrated in FIG. 10. It is evident from FIG. 10 that relative to the negative half wave with a variation in the input code of the corresponding D/A converter all conversion elements, which were previously activated, change their state with a transition to the following input code, while relative to the positive half wave with a variation of input code there are conversion elements, which do not change their state. Thus, for example, with a variation of the input code “5” to the input code “6” there are four conversion elements, that is to say the first four conversion elements of the D/A converter, which maintain their activated state. The number of conversion elements, which do not change their state, is even greater with a variation of the input code from “6” to “7”. Asymmetry linked with switching the conversion elements or the different rise and fall times leads to the fact that dependent on the particular input code an error arises in the output signal of the D/A converter, which leads to harmonic distortion (in particular of even-number order).
Generally, it can be stated that in the case of a time-continuous D/A converter, which is operated with a “dynamic element matching” algorithm, any asymmetry regarding the state changes of the individual conversion elements is converted into non-linear distortion. For suppressing this error with a variation from one input code to another input code of the D/A converter a “return to zero” codification can be implemented, which however requires a critical path for controlling the timing and moreover due to the necessary dead time leads to the energy of the output pulses being reduced.
Therefore an object of the present invention is to provide a method for digital/analog conversion as well as a digital/analog converter device configured accordingly, with which the problems described above can be eliminated, that is to say also when using a “dynamic element matching” algorithm, particularly a “data weighted averaging” algorithm, non-linear distortion in the analog output signal obtained by the digital/analog conversion can be reduced.